module cam(
  input                   clk,
  input                   reset_n,

  input  [ADDR_WIDTH-1:0] addr,
  input                   wr_en,
  input  [DATA_WIDTH-1:0] wdata,
  input                   rd_en,
  output [DATA_WIDTH-1:0] rdata,

  input                   search_en,
  input  [ADDR_WIDTH-1:0] search_content,
  output [DATA_WIDTH-1:0] search_addr
);

reg [DATA_WIDTH-1:0] memory[MEM_DEPTH];

always@(posedge clk)begin
  memory[addr] <= wdata;
end

assign rdata = memory[addr];

always@(posedge clk, negedge reset_n) begin
  if(reset_n)
    content_addr <= 'h0;
  else if(search_en)
    content_addr <= 'h0;
end

for(reg i; i++;i<DATA_WIDTH)begin
  if(memory[i] == search_content)begin
    search_addr = i;
  end
end

endmodule
